In general, as a semiconductor device becomes highly integrated, approaches for realizing a nano-technology in a manufacturing of the semiconductor device have been developed. However, a tool or a material of lithography using, particularly, a deep ultraviolet (DUV) equipment, is recently insufficient in view of a mass production and thus a size of a diameter of a wafer is enlarged. In addition, the purchase cost of the tool and a process costs are excessively increased.
For example, U.S. Pat. No. 6,346,467 discloses a method of making tungsten gate MOS transistor and memory cell by encapsulation and U.S. Patent Application Publication No. US2002/0001935 A1 discloses a method of forming a gate electrode in a semiconductor device which can prevent transformation of the gate electrode.
However, in such examples, when a fine transistor having a size of not greater than 0.10 μm is manufactured, there are limitations and drawbacks in forming a gate electrode having a small critical dimension. Particularly, as the critical dimension of the gate electrode is reduced, a short channel effect, in which a threshold voltage becomes small due to a shorter length between a source channel and a drain channel, occurs.